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1 Megabit Serial Flash
SST45LF010
SST45LF0101Mb Serial Architecture Interface flash memory
Data Sheet
FEATURES:
* * * * Single 3.0-3.6V Read and Write Operations Serial Interface Architecture Byte Serial Read with Single Command Superior Reliability - Endurance: 100,000 Cycles (typical) - Greater than 100 years Data Retention * Low Power Consumption - Active Current: 10 mA (typical) - Standby Current: 10 A (typical) * Sector or Chip-Erase Capability - Uniform 4 KByte sectors * Fast Erase and Byte-Program - Chip-Erase Time: 70 ms (typical) - Sector-Erase Time: 18 ms (typical) - Byte-Program Time: 14 s (typical) * Automatic Write Timing - Internal VPP Generation * End-of-Write Detection - Software Status * 10 MHz Max Clock Frequency * Hardware Reset Pin (RST#) - Resets the device to Standby Mode * CMOS I/O Compatibility * Hardware Data Protection (WP#) - Protects and unprotects the device from Write operation * Packages Available - 8-lead SOIC (4.9mm x 6mm) - 8-contact WSON
PRODUCT DESCRIPTION
The SST45LF010 is a 1 Mbit serial flash memory manufactured with SST's proprietary, high performance CMOS SuperFlash technology. The 1 Mbit of memory is organized as 32 sectors of 4096 Bytes. The flash memory uses a 3wire serial interface and a chip enable to select and sequentially access its data. The serial interface consists of; serial data input (SI), serial data output (SO), serial clock (SCK), and chip enable (CE#). A write protect (WP#) inhibits the entire memory from write operation and a hardware reset pin (RST#) resets the device to standby mode. The SST45LF010 device is offered in both 8-lead SOIC and 8-contact WSON packages. See Figure 1 for the pinouts.
Read
The Read operation outputs the data in order from the initial accessed address. While SCK is input, the address will be incremented automatically until end (top) of the address space (1FFFFH), then the internal address pointer automatically increments to beginning (bottom) of the address space (00000H), and data out stream will continue. The read data stream is continuous through all addresses until terminated by a low to high transition on CE#.
Sector/Chip-Erase Operation
The Sector-Erase operation clears all bits in the selected sector to FFH. The Chip-Erase instruction clears all bits in the device to FFH.
Device Operation
The SST45LF010 uses bus cycles of 8 bits each for commands, data, and addresses to execute operations. The operation instructions are listed in Table 3. All instructions are synchronized off a high to low transition of CE#. The first low to high transition on SCK will initiate the instruction sequence. Inputs will be accepted on the rising edge of SCK starting with the most significant bit. Any low to high transition on CE# before the input instruction completes will terminate any instruction in progress and return the device to the standby mode.
Byte-Program Operation
The Byte-Program operation programs the bits in the selected byte to the desired data. The selected byte must be in the erased state (FFH) when initiating a Program operation. The data is input from bit 7 to bit 0 in order.
Software Status Operation
The Status operation determines if an Erase or Program operation is in progress. If bit 0 is at a "0" an Erase or Program operation is in progress, the device is busy. If bit 0 is at a "1" the device is ready for any valid operation. The status read is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice.
(c)2001 Silicon Storage Technology, Inc. S71128-03-000 4/01 372 1
1 Megabit Serial Flash SST45LF010
Data Sheet
Reset
Reset will terminate any operation, e.g., Read, Erase and Program, in progress. It is activated by a high to low transition on the RST# pin. The device will remain in reset condition as long as RST# is low. Minimum reset time is 10 s. See Figure 14 for reset timing diagram. RST# is internally pulled-up and could remain unconnected during normal operation. After reset, the device is in standby mode, a high to low transition on CE# is required to start the next operation. An internal power-on reset circuit protects against accidental data writes. Applying a logic level low to RST# during the power-on process then changing to a logic level high when VDD has reached the correct voltage level will provide additional protection against accidental writes during power on.
TABLE 1: PRODUCT IDENTIFICATION
Byte Manufacturer's ID Device ID 0000H 0001H Data BFH 42H
T1.2 372
Write Protect
The WP# pin provides inadvertent write protection. The WP# pin must be held high for any Erase or Program operation. The WP# pin is "Don't Care" for all other operations. In typical use, the WP# pin is connected to VSS with a standard pull-down resistor. WP# is then driven high whenever an Erase or Program operation is required. If the WP# pin is tied to VDD with a pull-up resistor, then all operations may occur and the write protection feature is disabled. The WP# pin has an internal pull-up and could remain unconnected when not used.
Read SST ID/Read Device ID
The Read SST ID and Read Device ID operations read the JEDEC assigned manufacturer identification and the manufacturer assigned device identification IDs. These IDs may be used to determine the actual device resident in the system.
FUNCTIONAL BLOCK DIAGRAM
Address Buffers and Latches
X - Decoder
SuperFlash Memory
Y - Decoder
Control Logic
I/O Buffers and Data Latches
Serial Interface
CE#
(c)2001 Silicon Storage Technology, Inc.
SCK
SI
SO
2
WP#
RST#
372 ILL B1.4
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Data Sheet
WP# VDD CE# SCK
1 2
8 7
RST# VSS SO SI
WP# VDD CE# SCK
1
8
RST# VSS SO SI
2
7
Top View
3 4 6 5
Top View
3 6
4
5
372 ILL F01.6
372 ILL F01a.2
8-LEAD SOIC
8-CONTACT WSON
FIGURE 1: PIN ASSIGNMENTS TABLE 2: PIN DESCRIPTION
Symbol Pin Name SCK Serial Clock Functions To provide the timing of the serial interface. Commands, addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input. To transfer commands, addresses, or data serially into the device. Inputs are latched on the rising edge of the serial clock. To transfer data serially out of the device. Data is shifted out on the falling edge of the serial clock. The device is enabled by a high to low transition on CE#. To protect the device from unintentional Write (Erase or Program) operations. When WP# is low, all Erase and Program commands are ignored. When WP# is high, the device may be erased or programmed. This pin has an internal pull-up and could remain unconnected when not used. A high to low transition on RST# will terminate any operation in progress and reset the internal logic to the standby mode. The device will remain in the reset condition as long as the RST# is low. Operations may only occur when RST# is high. This pin has an internal pull-up and could remain unconnected when not used. To provide power supply (3.0-3.6V).
T2.5 372
SI SO CE# WP#
Serial Data Input Serial Data Output Chip Enable Write Protect
RST#
Reset
VDD VSS
Power Supply Ground
(c)2001 Silicon Storage Technology, Inc.
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1 Megabit Serial Flash SST45LF010
Data Sheet TABLE 3: DEVICE OPERATION INSTRUCTIONS1
Bus Cycle2 Cycle Type/ Operation3,4 Read Sector-Erase5 Chip-Erase Byte-Program Status Reg. Read-ID
1. 2. 3. 4. 5. 6. 7. 8.
1 SIN FFH 20H 60H 10H 9FH 90H SOUT Hi-Z Hi-Z Hi-Z Hi-Z X Hi-Z SIN
2 SOUT Hi-Z Hi-Z Hi-Z Hi-Z DOUT Hi-Z SIN
3 SOUT Hi-Z Hi-Z Hi-Z Hi-Z
Note6
4 SIN A7-A0 X X A7-A0 X ID Addr7 SOUT Hi-Z Hi-Z Hi-Z Hi-Z
Note6
5 SIN X D0H D0H DIN X X SOUT Hi-Z Hi-Z Hi-Z Hi-Z
Note6
6 SIN X X X X X X SOUT Hi-Z Hi-Z Hi-Z Hi-Z
Note6 Note8
7 SIN X X X X X X SOUT DOUT Hi-Z Hi-Z Hi-Z
Note6 Note8
T3.10 372
A23-A16 A23-A16 X A23-A16 X 00H
A15-A8 A15-A8 X A15-A8 X 00H
Hi-Z
Hi-Z
DOUT7
For SST45LF010, A23-A17 are "Don't Care." One bus cycle is eight clock periods Operation: SIN=Serial In, SOUT=Serial Out X=Dummy cycles (Don't Care) A16-A12 are used to determine sector address, A11-A8 are "Don't Care." The status read is continuous with ongoing clock cycles until terminated by a low to high transition on CE#. Manufacturer's ID=BFH, is read with A0 =0 and Device ID = 42H, is read with A0 =1; All other address bits are 0 The data output is arbitrary.
TABLE 4: DEVICE OPERATION TABLE
Operation Read Sector-Erase Chip-Erase Byte-Program Software-Status Reset2 Read SST ID Read Device ID SI X X X DIN X X X X SO DOUT X X X DOUT X DOUT DOUT CE#1 Low Low Low Low Low X Low Low WP# X High High High X X X X RST# High High High High High Low High High
T4.6 372
1. A high to low transition on CE# will be required to start any device operation except for Reset. 2. The RST# low will return the device to standby and terminate any Erase or Program operation in progress.
(c)2001 Silicon Storage Technology, Inc.
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1 Megabit Serial Flash SST45LF010
Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD+1.0V Package Power Dissipation Capability (Ta = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240C Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE
Range Commercial Ambient Temp 0C to +70C VDD 3.3V0.3V
AC CONDITIONS
OF
TEST
Input Rise/Fall Time . . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF
See Figures 2 and 3 TABLE 5: DC OPERATING CHARACTERISTICS VDD = 3.0-3.6V
Limits Symbol IDD Parameter Power Supply Current Read Program and Erase ISB ILI ILO IIL VIL VIH VIHC VOL VOH Standby Current Input Leakage Current Output Leakage Current Input Low Current1 Input Low Voltage Input High Voltage Input High Voltage (CMOS) Output Low Voltage Output High Voltage VDD-0.2 0.7 VDD VDD-0.3 0.2 20 30 15 1 1 360 0.8 mA mA A A A A V V V V V Min Max Units Test Conditions f=10 MHz CE#=VIL, VDD=VDD Max CE#=VIL, VDD=VDD Max CE#=VIHC, VDD=VDD Max VIN=GND to VDD, VDD=VDD Max VOUT =GND to VDD, VDD=VDD Max WP#, RST#=GND VDD=VDD Min VDD=VDD Max VDD=VDD Max IOL=100 A, VDD=VDD Min IOH=-100 A, VDD=VDD Min
T5.1 372
1. This parameter only applies to WP# and RST# pins.
(c)2001 Silicon Storage Technology, Inc.
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1 Megabit Serial Flash SST45LF010
Data Sheet TABLE 6: CAPACITANCE
Parameter COUT1 CIN
1
(Ta = 25C, f=1 Mhz, other pins open)
Description Output Pin Capacitance Input Capacitance
Test Condition VOUT = 0V VIN = 0V
Maximum 12 pF 6 pF
T6.1 372
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 7: RELIABILITY CHARACTERISTICS
Symbol NEND1 TDR1 ILTH1 Parameter Endurance Data Retention Latch Up Minimum Specification 10,000 100 100 + IDD Units Cycles Years mA Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard 78
T7.1 372
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 8: AC OPERATING CHARACTERISTICS, VDD = 3.0-3.6V
Limits Symbol FCLK TSCKH TSCKL TCES TCEH TCPH TCHZ TCLZ TRLZ TDS TDH TOH TV TWPS TWPH TSE TSCE TBP TRST TREC TPURST Parameter Serial Clock Frequency Serial Clock High Time Serial Clock Low Time CE# Setup Time CE# Hold Time CE# High Time CE# High to High-Z Output SCK Low to Low-Z Output RST# Low to High-Z Output Data In Setup Time Data In Hold Time Output Hold from SCK Change Output Valid from SCK Write Protect Setup Time Write Protect Hold Time Sector-Erase Chip-Erase Byte-Program Reset Pulse Width Reset Recovery Time Reset Time After Power-Up 10 10 1 10 10 25 100 20 20 20 0 35 0 25 45 45 250 250 250 25 Min Max 10 Units MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms s s s s
T8.2 372
(c)2001 Silicon Storage Technology, Inc.
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1 Megabit Serial Flash SST45LF010
Data Sheet
VIHT
INPUT
VIT
REFERENCE POINTS
VOT
OUTPUT
VILT
372 ILL F02.2
AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and VILT (0.1 VDD) for a logic "0". Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% 90%) are <5 ns.
Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test
FIGURE 2: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TO TESTER
TO DUT CL
372 ILL F03.2
FIGURE 3: A TEST LOAD EXAMPLE
(c)2001 Silicon Storage Technology, Inc.
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1 Megabit Serial Flash SST45LF010
Data Sheet
WP# TCPH CE# TCES SCK TDS SI TDH TSCKH TSCKL TCEH
DATA VALID HIGH-Z HIGH-Z
372 ILL F04.6
SO
FIGURE 4: SERIAL INPUT TIMING DIAGRAM (INACTIVE SERIAL CLOCK LOW)
WP#
CE# TSCKH TSCKL SCK TCLZ SO TV SI
372 ILL F05.6
TCEH
TOH DATA VALID
TCHZ
FIGURE 5: SERIAL OUTPUT TIMING DIAGRAM (INACTIVE SERIAL CLOCK LOW)
(c)2001 Silicon Storage Technology, Inc.
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1 Megabit Serial Flash SST45LF010
Data Sheet
TWPS WP#
TWPH
CE# TSE 012345 SCK 678 15 16 23 24 31 32 39 40 47
SELF-TIMED SECTORERASE CYCLE
SI
20H
ADD.
ADD.
X
D0H
X
SO
HIGH IMPEDANCE
372 ILL F06.7
FIGURE 6: SECTOR-ERASE TIMING DIAGRAM
TWPS WP#
TWPH
CE# TSCE 012345 SCK 678 15 16 23 24 31 32 39 40 47
SELF-TIMED CHIPERASE CYCLE
SI
60H
X
X
X
D0H
X
SO
HIGH IMPEDANCE
372 ILL F07.10
FIGURE 7: CHIP-ERASE TIMING DIAGRAM
(c)2001 Silicon Storage Technology, Inc.
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1 Megabit Serial Flash SST45LF010
Data Sheet
TWPS WP#
TWPH
CE# 012345 SCK 678 15 16 23 24 31 32 39 40 47 TBP
SELF-TIMED BYTEPROGRAM CYCLE
SI
10H
ADD.
ADD.
ADD. MSB
Din LSB
X
SO
HIGH IMPEDANCE
372 ILL F08.8
FIGURE 8: BYTE-PROGRAM TIMING DIAGRAM
WP#
CE# 012345 SCK 678 15 16 23 24 31 32 39 40 47 48 55 56 63 64 71
SI
FFH
ADD.
ADD.
ADD.
X
X N Dout MSB N+1 Dout MSB N+2 Dout MSB
372 ILL F10.6
SO
HIGH IMPEDANCE
FIGURE 9: READ TIMING DIAGRAM
(c)2001 Silicon Storage Technology, Inc.
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1 Megabit Serial Flash SST45LF010
Data Sheet
WP#
CE# 012345 SCK 678 15 16 23 24 31 32 39 40 47 48 55 56 63 64 71
SI
90H
00H
00H
ADD1
SO
HIGH IMPEDANCE
Dout1 MSB LSB
372 ILL F19.4
Note: 1. SST Manufacturer's ID = BFH is read with A0=0 SST45LF010 Device ID = 42H is read with A0=1
FIGURE 10: READ-ID TIMING DIAGRAM
WP#
CE# 012345 SCK 678 9 10 11 12 13 14 15 16 23 24 31
SI
9FH
SO
HIGH IMPEDANCE MSB
DATA
DATA MSB
DATA MSB
372 ILL F11.5
FIGURE 11: SOFTWARE-STATUS TIMING DIAGRAM
(c)2001 Silicon Storage Technology, Inc.
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1 Megabit Serial Flash SST45LF010
Data Sheet
CE# TREC SCK TCES
...
TRST
RESET#
HIGH IMPEDANCE SO
... ...
TRLZ
HIGH IMPEDANCE
SI
372 ILL F20.4
FIGURE 12: RESET TIMING DIAGRAM (INACTIVE CLOCK POLARITY LOW)
VDD TPURST
RESET# TREC CE#
372 ILL F13.3
FIGURE 13: POWER-ON RESET TIMING DIAGRAM
TWPS WP#
TWPH
TCPH CE# TCES SCK
372 ILL F14.1
TCEH
FIGURE 14: WRITE PROTECT TIMING DIAGRAM
(c)2001 Silicon Storage Technology, Inc. S71128-03-000 4/01 372
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1 Megabit Serial Flash SST45LF010
Data Sheet Device SST45LFxxx Speed - XXX Suffix1 XX Suffix2 XX Package Modifier A = 8 leads Package Type S = SOIC Q = WSON Temperature Range C = Commercial = 0C to +70C Minimum Endurance 4 = 10,000 cycles Operating Frequency 10 = 10 MHz Device Density 010 = 1 Megabit Voltage L = 3.0-3.6V
SST45LF010 Valid combinations SST45LF010-10-4C-SA
Example:
SST45LF010-10-4C-QA
Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.
(c)2001 Silicon Storage Technology, Inc.
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1 Megabit Serial Flash SST45LF010
Data Sheet
PACKAGING DIAGRAMS
Pin #1 Identifier
Top View
Side View
7 4 places
5.0 4.8
.51 .33
1.27 BSC
End View
45
4.00 3.80 6.20 5.80 1.75 1.35 0.25 0.10 7 4 places
0.25 0.19 0 1.27 0.40
Note:
1. Complies with JEDEC publication 95 MS-012 AA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (.05) mm. 4. Maximum allowable mold flash is 0.15 mm at the package ends and 0.25 mm between leads.
8
08.soic-SA-ILL.5
8-LEAD SMALL OUTLINE INTEGRATED CIRCUIT PACKAGE (SOIC) SST PACKAGE CODE: SA
Pin #1 Corner
Top View
Side View
.19 .25
Bottom View
Pin #1
1.27 BSC
4.00 5.00 BSC .076 3.40 .35 .48
6.00 BSC .70 .80
.05 Max
.50 .75
Cross Section
.70 .80
Note: 1. All linear dimensions are in millimeters (min/max).
8-wson-5x6-QA-ILL.4
8-CONTACT ULTRA-THIN SMALL OUTLINE NO-LEAD PACKAGE (WSON) SST PACKAGE CODE: QA
Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.ssti.com
(c)2001 Silicon Storage Technology, Inc. S71128-03-000 4/01 372
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